Computer-Aided Digital System Design (CAD)!

“A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development” By John L. Hennessy and David A. Patterson

1.Introductions and basic concepts

  • History of digital systems
  • Investigating the Growth of Digital Systems Design Industry
  • Hardware automation design tools and languages
  • ASIC and FPGA design cycles and their comparisons
  • Hardware design styles
  • Abstract levels of hardware design

2.Hardware description languages

  • Reasons for the need for hardware description languages versus schematic methods
  • Key features of a hardware description language
  • Conjugation as a prominent feature of hardware description languages
  • Conventional hardware description languages and their comparisons
  • Verilog / VHDL language features
  • Compare VHDL / Verilog with other hardware description languages
  • Hardware Simulation Techniques

3. VHDL / Verilog Description Language Learning

  • The language of instruction is taught in this section. The time taken for this section is approximately 4 to 6 weeks. It is recommended that descriptive language training be provided with illustrative examples applied. This section includes the following.
  • Delay model in target language
  • Language data types
  • Hardware description method at different levels (behavioral, data flow and structural)
  • Specific features of the desired description language
  • Testbench design method
  • Design of sequential and hybrid functional blocks with the desired language
  • Parametric or generic design
  • Large hardware complexity management methods
  • Descriptive organizing techniques
  • Top-down design method and bottom-up design method
  • Types of state machine description methods with hardware description language and state coding methods (binary, ont-hot, coding)
  • Design of pipeline and how to describe it at the level of stability transmission

4.Hardware synthesis

  • Concepts of behavioral, logical and physical synthesis
  • The steps to perform a rational synthesis
  • 1.Non-technology-dependent stage
  • 2.Technology-related step (Technology mapping)
  • The concept of a synthesized subset and the considerations needed in describing a synthesized
  • Simulation and testing after synthesis
  • Constraint based design
  • Static time analysis (STA) methods and Slack parameter introduction
  • How to optimize design criteria (speed, area and power consumption) using tools
  • A review of high-power and low-power circuit design techniques
  • A review of testable orbital design techniques

5.Design of digital systems with PLD (at least 6 weeks)

  • An overview of the types of PLDs, applications of PLDs in research and industry, and the internal structure of PLDs (logic block architecture and IO block architecture, connection architecture)
  • Useful resources in the structure of existing PLDs (DCM, Gigabit Transceiver, DSP blocks, latent processors, etc.) and their application
  • SPLDs and CPLDs
  • FPGAs and their structure
  • Hardware design and synthesis methods for mapping to FPGAs